The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to correlation of data communicated over multiple communication links.
To validate or debug components of a computer system, a logic analyzer may be used to capture and analyze data exchanged between the components. Some components may utilize multiple communication links or interfaces, and the traffic occurring on the various interfaces may interact. Hence, validation and debug of such components may require knowledge of the traffic that is simultaneously occurring on the multiple interfaces.
Moreover, separate logic analyzers may be used to capture the data communicated via each interface. However, correlating the data captured from the different interfaces may be difficult to achieve, in part, due to timing differences. More particularly, depending on system load, data communicated over different interfaces at the same time may be captured at different times. Also, as data propagates through additional interfaces, the time difference may further deviate from the actual time.
Alternatively, a single logic analyzer may be used to capture and correlate data from different interfaces of a system. However, single logic analyzer implementations may involve the use of a costly logic analysis system (e.g., a mainframe system) that may not interoperate with other types of trace capture systems.